High Speed GMLAN Circuit Description
| Callout | Component Name |
|---|---|
| DD | Serial Data - GMLAN High Speed |
| DD | Serial Data - GMLAN High Speed |
| DD | Serial Data - GMLAN High Speed |
| DD | Serial Data - GMLAN High Speed |
| DD | Serial Data - GMLAN High Speed |
| DD | Serial Data - GMLAN High Speed |
| DD | Serial Data - GMLAN High Speed |
| DD | Serial Data - GMLAN High Speed |
| NJ2 | STEERING: ELECTRIC, BELT DRIVE |
| NXC | STEERING: POWER, VARIABLE EFFORT, REDUCED RACK TRAVEL |
| TR7 | CONTROL, HEADLAMPS: LEVELING SYSTEM, AUTOMATIC |
| T95 | CONTROL, HEADLAMPS: BEAM, DIRECTIONAL (AFL) |
| F38 | CHASSIS: REAR, AIR, INCREASED RIDE |
| F55 | CHASSIS: CONTINOUSLY VARIABLE REAL TIME DAMPING MAGNETO RHEOLOGICAL |
| UGN | COLL IMMINENT BRK: VEHICLE FORWARD MOVEMENT, BRAKE PREFILL and INTELLIGENT BRAKE ASSIST |
| UVZ | SENSOR: COLLISION AVOIDANCE and MITIGATION, VEHICLE REVERSE MOVEMENT |
| F46 | CHASSIS: ALL WHEEL DRIVE (AWD) |
| UE1 | COMMUNICATION SYSTEM: VEHICLE, ONSTAR |
| UQS | SPEAKER SYSTEM: PREMIUM AUDIO BRANDED WITH SURROUND AMPLIFIER |
| K20 | K20 Engine Control Module |
| K71 | K71 Transmission Control Module |
| K43 | K43 Power Steering Control Module |
| K43 | K43 Power Steering Control Module |
| K26 | K26 Headlamp Control Module |
| K17 | K17 Electronic Brake Control Module |
| K9 | K9 Body Control Module |
| K83 | K83 Park Brake Control Module |
| K19 | K19 Suspension Control Module |
| K124 | Active Safety Control Module |
| K47 | K47 Rear Differential Clutch Control Module |
| K73 | K73 Telematics Communication Interface Control Module |
| K38 | K38 Chassis Control Module |
| K74 | Human Machine Interface Control Module |
| T3 | T3 Audio Amplifier |
| X84 | X84 Data Link Connector |
A High Speed GMLAN Bus is used where data needs to be exchanged at a high enough rate to minimize the delay between the occurrence of a change in sensor value and the reception of this information by a control device using the information to adjust vehicle system performance.
The High Speed GMLAN serial data network consists of two twisted wires. One signal circuit is identified as GMLAN-High and the other signal circuit is identified as GMLAN-Low. At each end of the data bus there is a 120 Ω termination resistor between the GMLAN-High and GMLAN-Low circuits.
Data symbols (1's and 0's) are transmitted sequentially at a rate of 500 Kbit/s. The data to be transmitted over the bus is represented by the voltage difference between the GMLAN-High signal voltage and the GMLAN-Low signal voltage.
When the two wire bus is at rest the GMLAN-High and GMLAN-Low signal circuits are not being driven and this represents a logic "1". In this state both signal circuits are at the same voltage of 2.5 V. The differential voltage is approximately 0 V.
When a logic "0" is to be transmitted, the GMLAN-High signal circuit is driven higher to about 3.5 V and the GMLAN-Low circuit is driven lower to about 1.5 V. The differential voltage becomes approximately 2.0 (+/- 0.5) V.
Devices on High Speed GMLAN Bus enable or disable communication based on the voltage level of the communication enable circuit. When the circuit voltage is high (around 12 V), communications are enabled. When the circuit is low, communications are disabled.